EE 4303b -- New Course

Wed Sep 22 12:37:56 2010

Approvals Received:
Department
on 09-22-10
by Kyle Dukart
(kdukart@umn.edu)
Approvals Pending: College/Dean  > Catalog > PeopleSoft Manual Entry
Effective Status: Active
Effective Term: 1109 - Fall 2010
Course: EE 4303
Institution:
Campus:
UMNTC - Twin Cities
UMNTC - Twin Cities
Career: UGRD
College: TIOT - College of Science and Engineering
Department: 11122 - Electrical & Computer Eng
General
Course Title Short: Intro to Programmable Devices
Course Title Long: Introduction to Programmable Devices Laboratory
Max-Min Credits
for Course:
1.0 to 1.0 credit(s)
Catalog
Description:
Introduction to the Verilog Language. Combinatorial and sequential logic synthesis with Verilog. Implementation in Field Programmable Gate Arrays (FPGAs). Cannot receive credit for 4303 if credit granted for EE 4301.
Print in Catalog?: Yes
CCE Catalog
Description:
<no text provided>
Grading Basis: Stdnt Opt
Topics Course: No
Honors Course: No
Delivery Mode(s): Classroom
Instructor
Contact Hours:
3.0 hours per week
Years most
frequently offered:
Every academic year
Term(s) most
frequently offered:
Spring
Component 1: LAB (no final exam)
Auto-Enroll
Course:
No
Graded
Component:
LAB
Academic
Progress Units:
Not allowed to bypass limits.
1.0 credit(s)
Financial Aid
Progress Units:
Not allowed to bypass limits.
1.0 credit(s)
Repetition of
Course:
Repetition not allowed.
Course
Prerequisites
for Catalog:
EE 2301, EE 2361
Course
Equivalency:
EE 4301
Consent
Requirement:
No required consent
Enforced
Prerequisites:
(course-based or
non-course-based)
EE 2301 and EE 2361
Editor Comments: <no text provided>
Proposal Changes: <no text provided>
History Information: <no text provided>
Faculty
Sponsor Name:
Thomas Posbergh
Faculty
Sponsor E-mail Address:
posbergh@umn.edu
Student Learning Outcomes
Student Learning Outcomes: * Student in the course:

- Can identify, define, and solve problems

Please explain briefly how this outcome will be addressed in the course. Give brief examples of class work related to the outcome.

Through a series of hands-on labs students will learn how to formulate and document logic design problems in the Verilog Hardware Definition Language, evaluate them through simulation, and use a hardware synthesis tool to implement the design on an FPGA.

How will you assess the students' learning related to this outcome? Give brief examples of how class work related to the outcome will be evaluated.

Student performance will be assessed with online Moodle quizzes and two formal lab reports.

- Can communicate effectively

Please explain briefly how this outcome will be addressed in the course. Give brief examples of class work related to the outcome.

Two formal written lab reports are required. Moveover, clearly written Verilog code which documents the logic design will be required in each lab.

How will you assess the students' learning related to this outcome? Give brief examples of how class work related to the outcome will be evaluated.

The two formal written lab reports will be graded based on presentation as well as results. The instructor will provide feedback on the Verilog code written by the students for the labs. The Velilog code willl also be graded as part of the formal lab report.

Liberal Education
Requirement
this course fulfills:
None
Other requirement
this course fulfills:
None
Criteria for
Core Courses:
Describe how the course meets the specific bullet points for the proposed core requirement. Give concrete and detailed examples for the course syllabus, detailed outline, laboratory material, student projects, or other instructional materials or method.

Core courses must meet the following requirements:

  • They explicitly help students understand what liberal education is, how the content and the substance of this course enhance a liberal education, and what this means for them as students and as citizens.
  • They employ teaching and learning strategies that engage students with doing the work of the field, not just reading about it.
  • They include small group experiences (such as discussion sections or labs) and use writing as appropriate to the discipline to help students learn and reflect on their learning.
  • They do not (except in rare and clearly justified cases) have prerequisites beyond the University's entrance requirements.
  • They are offered on a regular schedule.
  • They are taught by regular faculty or under exceptional circumstances by instructors on continuing appointments. Departments proposing instructors other than regular faculty must provide documentation of how such instructors will be trained and supervised to ensure consistency and continuity in courses.

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Criteria for
Theme Courses:
Describe how the course meets the specific bullet points for the proposed theme requirement. Give concrete and detailed examples for the course syllabus, detailed outline, laboratory material, student projects, or other instructional materials or methods.

Theme courses have the common goal of cultivating in students a number of habits of mind:
  • thinking ethically about important challenges facing our society and world;
  • reflecting on the shared sense of responsibility required to build and maintain community;
  • connecting knowledge and practice;
  • fostering a stronger sense of our roles as historical agents.


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Writing Intensive
Propose this course
as Writing Intensive
curriculum:
No
Question 1: What types of writing (e.g., reading essay, formal lab reports, journaling) are likely to be assigned? Include the page total for each writing assignment. Indicate which assignment(s) students will be required to revise and resubmit after feedback by the instructor or the graduate TA.

<no text provided>
Question 2: How does assigning a significant amount of writing serve the purpose of this course?

<no text provided>
Question 3: What types of instruction will students receive on the writing aspect of the assignments?

<no text provided>
Question 4: How will the students' grades depend on their writing performance? What percentage of the overall grade will be dependent on the quality and level of the students' writing compared with the course content?

<no text provided>
Question 5: If graduate students or peer tutors will be assisting in this course, what role will they play in regard to teaching writing?

<no text provided>
Question 6: How will the assistants be trained and supervised?

<no text provided>
Question 7: Write up a sample assignment handout here for a paper that students will revise and resubmit after receiving feedback on the initial draft.

<no text provided>
Course Syllabus
Course Syllabus: For new courses and courses in which changes in content and/or description and/or credits are proposed, please provide a syllabus that includes the following information: course goals and description; format;structure of the course (proposed number of instructor contact hours per week, student workload effort per week, etc.); topics to be covered; scope and nature of assigned readings (text, authors, frequency, amount per week); required course assignments; nature of any student projects; and how students will be evaluated. The University "Syllabi Policy" can be found here

The University policy on credits is found under Section 4A of "Standards for Semester Conversion" found here. Course syllabus information will be retained in this system until new syllabus information is entered with the next major course modification. This course syllabus information may not correspond to the course as offered in a particular semester.

(Please limit text to about 12 pages. Text copied and pasted from other sources will not retain formatting and special characters might not copy properly.)


EE4303 --- Introduction to Programmable Logic Devices Laboratory
Course Webpage:
This course will use Moodle
Text:
Michael Ciletti, Starter's guide to Verilog 2001, Pearson/Prentice-Hall, 2004
In addition to the text we will make extensive use of online resources
Prerequisites: EE2301 and EE2361
Grading Components:
lab quizzes (online): 10%
first lab report: 30%
final lab report: 60%
All labs need to be completed and all lab reports turned in to pass this course
Schedule:
Lab 1 Compiling Verilog Code with the Xilinx IDE (1.0 week)
Lab 2 HDL entry (1.0 week)
Lab 3 Schematic capture (1.0 week)
Lab 4 FPGA implementation (1.5 week)
(first lab report due)
Lab 5 Counters (2.5 week)
Lab 6 State Machines (part 1: datapaths) (2.0 week)
Lab 7 State Machines (part 2: controllers) (2.0 week)
Lab 8 Optimizing the implementation (1.5 week)
(final lab report due)
Note there is a week and half slack at the end of the labs as some labs might
take longer.